Was asked about questions related to my projects. And topics related to timing analysis, digital electronics, computer architecture etc.
Soc Design Engineer Interview Questions
114 soc design engineer interview questions shared by candidates
How would you verify a Verilog design?
1. What motivates and frustrates you? 2. Many coding questions
Describe logic gates AND, OR, XOR
The basic RTL coding such as non blocking & blocking.
How to swap two registers in verilog without using third register?
Different multiplexer and demultiplexer and describe the function application.
Describe what is PCIe and the protocol.
How many type of multiplexer and what is the application. Explain how 2 to 1 multiplexer with 9 input.
1. what are inertial delay and transport delay? 2. Circuit using D latch, master slave FF & explain it 3. how u will reduce the input frequency? draw the circuit & explain 4. D FF Verilog code
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